1. Field of the Invention
The present invention relates to a multiplier for multiplying two analog input signals, which is to be realized on a semiconductor integrated circuit device and more particularly, to an analog multiplier formed of bipolar transistors and/or metal-oxide-semiconductor field-effect transistors (MOSFETs), which can operate within an expanded input voltage range or ranges even at a low supply voltage such as 3 or 3.3 V.
2. Description of the Prior Art
An analog multiplier constitutes a functional circuit block essential for analog signal applications. Recently, semiconductor integrated circuits have been made finer and finer and as a result, their supply voltages have been decreasing from 5 V to 3.3 or 3 V.
Under such a circumstance, a low-voltage circuit technique that enables to operate at such a low voltage as 3 V has been required to be developed. In the case, the input voltage ranges of the multiplier need to be wide as much as possible.
The Gilbert multiplier cell is well known as a bipolar multiplier. However, the Gilbert multiplier cell has such a structure that bipolar transistor-pairs are stacked in two stages and as a result, it cannot respond to or cope with such the supply voltage reduction as above. Therefore, a new bipolar multiplier that can operate at such the low supply voltage has been expected instead of the Gilbert multiplier cell.
Besides, the Complementary MOS (CMOS) technology has become recognized to be the optimum process technology for Large Scale Integration (LSI), so that a new circuit technique that can realize a multiplier using the CMOS technology has been required.
To respond such the expectation as above, the inventor, Kimura, developed multipliers as shown in FIGS. 1, 4 and 7, each of which has two squaring circuits. One of the squaring circuits is applied with a differential input voltage (V1+V2), and the other thereof is applied with another differential input voltage (V2-V1), where V.sub.1 and V.sub.2 are input signal voltages to be multiplied. The outputs of these two squaring circuits are subtracted to generate an output voltage V.sub.OUT of the multiplier, which is expressed as EQU V.sub.OUT =(V.sub.1 +V.sub.2).sup.2 -(V.sub.2 -V.sub.1).sup.2 =4V.sub.1 .multidot.V.sub.2
From this equation, it is seen that the output voltage V.sub.OUT is proportional to the product V.sub.1 .multidot.V.sub.2 of the first input voltage V.sub.1 and the second input voltage V.sub.2, meaning that the circuit having the two squaring circuits provides a multiplier characteristic.
The squaring circuits are arranged along a straight line transversely not in stack, to be driven at the same supply voltage.
The above prior-art multipliers developed by Kimura were termed "quarter-square multipliers" since the constant "4" of involution contained in the term of the product was changed to "1".
Next, the Kimura's prior-art multipliers will be described below.
First, the Kimura's prior-art multiplier shown in FIG. 1 is disclosed in the Japanese Non-Examined Patent Publication No. 5-94552 (April, 1993). In FIG. 1, this multiplier includes a first squaring circuit made of bipolar transistors Q51, Q52, Q53 and Q54 and a second squaring circuit made of bipolar transistors Q55, Q56, Q57 and Q58.
In the first squaring circuit, the transistors Q51 and Q52 form a first unbalanced differential pair driven by a first constant current source (current :I.sub.0) and the transistors Q53 and Q54 form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor Q51 is K times in emitter area as large as the transistor Q52 and the transistor Q54 is K times in emitter area as large as the transistor Q53.
Emitters of the transistors Q51 and Q52 are connected in common to the first constant current source, and emitters of the transistors Q53 and Q54 are connected in common to the second constant current source.
In the second squaring circuit, the transistors Q55 and Q56 form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0) and the transistors Q57 and Q58 form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor Q55 is K times in emitter area as large as the transistor Q56 and the transistor Q58 is K times in emitter area as large as the transistor Q57.
Emitters of the transistors Q55 and Q56 are connected in common to the third constant current source, and emitters of the transistors Q57 and Q58 are connected in common to the fourth constant current source.
Bases of the transistors Q51 and Q53 are coupled together to be applied with a first input voltage V.sub.x, and bases of the transistors Q52 and Q54 are coupled together to be applied with a second input voltage V.sub.y.
Bases of the transistors Q55 and Q57 are coupled together to be applied with the first input voltage V.sub.x, and bases of the transistors Q56 and Q58 are coupled together to be applied in opposite phase with the second input voltage V.sub.y, or -V.sub.y.
The transfer characteristics and the transconductance characteristics of the multiplier of FIG. 1 are shown in FIGS. 2 and 3, respectively, where K is e.sup.2 (.apprxeq.7.389). A differential output current .DELTA.I shown in FIG. 2 is defined as the difference of output currents I.sub.p and I.sub.q shown in FIG. 1, or (I.sub.p -I.sub.q).
FIG. 2 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 3 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Second, the Kimura's prior-art multiplier shown in FIG. 4 is disclosed in the Japanese Non-Examined patent Publication No. 4-34673 (February, 1992). In FIG. 4, the multiplier includes a first squaring circuit made of MOS transistors M51, M52, M53 and M54 and a second squaring circuit made of MOS transistors M55, M56, M57 and M58.
In the first squaring circuit the transistors M51 and M52 form a first unbalanced differential pair driven by a first constant current source (current :I.sub.0), and the transistors M53 and M54 form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor M52 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M51, and the transistor M53 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M54.
Sources of the transistors M51 and M52 are connected in common to the first constant current source, and sources of the transistors M53 and M54 are connected in common to the second constant current source.
In the second squaring circuit, the transistors M55 and M56 form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0), and the transistors M57 and M58 form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor M56 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M55, and the transistor M57 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M58.
Sources of the transistors M55 and M56 are connected in common to the third constant current source, and sources of the transistors M57 and M58 are connected in common to the fourth constant current source.
Gates of the transistors M51 and M53 are coupled together to be applied with a first input voltage V.sub.x, and gates of the transistors M52 and M54 are coupled together to be applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y.
Gates of the transistors M55 and M57 are coupled together to be applied with the first input voltage V.sub.x, and gates of the transistors M56 and M58 are coupled together to be applied with the second input voltage V.sub.y.
In FIG. 4, the transconductance parameters of the transistors M51, M54, M55 and M58 are equal to be .beta., and those of the transistors M52, M53, M56 and M57 are equal to be K'.beta..
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 5 and 6, respectively, where K' is 5. A differential output current .DELTA.I shown in FIG. 5 is defined as the difference of output currents I.sup.+ and I.sup.- shown in FIG. 4, or (I.sup.+ -I.sup.-).
FIG. 5 shows the relationship between the differential output current .DELTA.I and the fist input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 6 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter
Third, the Kimura's prior-art multiplier shown in FIG. 7 is disclosed in IEICE TRANSACTIONS ON FUNDAMENTALS, Vol. E75-A, No. 12, December, 1992. In FIG. 7, the multiplier includes a first squaring circuit made of MOS transistors M61, M62, M63 and M64 and a first constant current source (current: I.sub.0) for driving the transistors M61, M62, M63 and M64, and a second squaring circuit made of MOS transistors M65, M66, M67 and M68 and a second constant current source (current: I.sub.0) for driving the transistors M65, M66, M67 and M68. The transistors M61, M62, M63, M64, M65, M66, M67 and M68 are equal in capacity or ratio (W/L) of a gate-width W to a gate-length L to each other.
The first and second squaring circuits are termed "quadritail circuits" or "quadritail cells" in which four transistors are driven by a common constant current source, respectively.
In the first quadritail circuit, sources of the transistors M61, M62, M63 and M64 are connected in common to the first constant current source. Drains of the transistors M61 and M62 are coupled together and drains of the transistors M63 and M64 are coupled together. A gate of the transistor M61 is applied with a first input voltage V.sub.x, and a gate of the transistor M62 is applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y. Gates of the transistor M63 and M64 are coupled together to be applied with the middle level of the voltage applied between the gates of the transistors M61 and M62, or (1/2)(V.sub.x +V.sub.y), which is obtained through resistors (resistance: R).
Similarly, In the second quadritail circuit, sources of the transistors M65, M66, M67 and M68 are connected in common to the second constant current source. Drains of the transistors M65 and M66 are coupled together and drains of the transistors M67 and M68 are coupled together. A gate of the transistor M65 is applied with the first input voltage V.sub.x, and a gate of the transistor M66 is applied with the second input voltage V.sub.y. Gates of the transistor M67 and M68 are coupled together to be applied with the middle level of the voltage applied between the gates of the transistors M65 and M66, or (1/2)(V.sub.x -V.sub.y), which is obtained through resistors (resistance: R).
Between the first and second quadritail circuits, the drains coupled together of the transistors M61 and M62 and the drains coupled together of the transistors M67 and M68 are further coupled together to form one of differential output ends of the multiplier. The drains coupled together of the transistors M63 and M64 and the drains coupled together of the transistors M65 and M66 are further coupled together to form the other of the differential output ends thereof.
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 8 and 9, respectively. A differential output current .DELTA.I shown in FIG. 8 is defined as the difference of output currents I.sub.P and I.sub.Q shown in FIG. 7, or (I.sub.p -I.sub.Q).
FIG. 8 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 9 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Further prior-art multiplier is shown in FIG. 10, which was developed by Wang and termed the "Wang cell". This is disclosed in IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September, 1991. The circuit in FIG. 10 is modified by the inventor, Kimura, to clarify its characteristics
In FIG. 10, the multiplier includes one quadritail circuit made of MOS transistors M71, M72, M73 and M74 and a constant current source (current: I.sub.0) for driving the transistors M71, M72, M73 and M74. The transistors M71, M72, M73 and M74 are equal in capacity (W/L) to each other.
Sources of the transistors M71, M72, M73 and M74 are connected in common to the constant current source. Drains of the transistors M71 and M74 are coupled together to form one of differential output ends of the multipliers and drains of the transistors M72 and M73 are coupled together to form the other of the differential output ends thereof.
A gate of the transistor M71 is applied with a first input voltage (1/2)V.sub.x based on a reference point, and a gate of the transistor M72 is applied in opposite polarity with the first input voltage V.sub.x, or -V.sub.x based on the reference point. A gate of the transistor M73 is applied with a voltage of the half difference of the first input voltage and a second input voltage, or (1/2)(V.sub.x -V.sub.y). A gate of the transistor M74 is applied with the voltage (1/2)(V.sub.x -V.sub.y) in opposite polarity, or (-1/2)(V.sub.x -V.sub.y).
The transfer characteristics and the transconductance characteristics of the Wang's multipliers which were obtained through analysis by the inventor, are shown in FIGS. 11 and 12, respectively. A differential output current .DELTA.I shown in FIG. 11 is defined as the difference of output currents I.sub.L and I.sub.R shown in FIG. 10, or (I.sub.L -I.sub.R).
FIG. 11 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 12 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
The prior-art bipolar multiplier of FIG. 1 has input voltage ranges that is approximately equal to those of the conventional Gilbert multiplier cell. Each of the prior-art MOS multipliers of FIGS. 4, 7 and 10 has input voltage ranges of superior linearity that is comparatively wider than those of the Gilbert multiplier cell.
However, on operating at a low supply voltage such as 3 or 3.3 V, all of the prior-art multipliers cannot expand their input voltage ranges of superior linearity due to causes relating their circuit configurations.